As data rates exceed 1 Gbps, new challenges arise for backplane system designers. Signal integrity is critical for data throughput levels in excess of 40 Gbps. Network processors (NPUs) provide a low-cost means of accelerating packet processing in communications equipment. However, today's NPUs are inflexible and lack the performance required for high-speed traffic. System interface standards address increasing bandwidth requirements between IC components, line cards, and systems. Developing systems interfaces consumes a considerable amount of time and engineering resources. Multiple interface support is often required as ASICs, ASSPs, memory, and microprocessors support different system interfaces that may involve older protocols. Switched architectures based on serial signaling technologies are required to address multi-gigabit backplanes.
In any conventional line card with a telecommunications system such as an add/drop multiplexer (ADM) or multi-service provisioning platform (MSPP), a framer and a mapper are provided separate from a host processor which controls their functionality. For example, the host processor may communicate with a shelf controller, while the shelf controller may communicate with a system controller. Alternatively, the host processor may communicate with a system controller if the system is small and a shelf controller is not required. As can be seen in FIG. 1, a block diagram of a conventional system for generating and outputting frames of data from a line card in a data communication network is shown. In particular, a conventional communication system 100 comprises a line card 102, coupled to a backplane 104, which communicates with a shelf/system controller 106 and/or a system controller 108. The line card comprises a framer 110, a mapper 112, and a switch/node point (NP) 114, each of which is coupled to a host processor 116. The system 100 could be, for example, a generic Packet over SONET(POS)/SDH line card typically found in a multi-service provisioning platform.
As can be seen in FIG. 1, the host processor is a separate component from the framer, mapper and switch. Therefore, while the card itself has intelligence (i.e. the host processor), the framer, mapper and switch do not. The framer, mapper and switch are dependent on the host processor for control. Because the controlling function is external to the framer, mapper and switch components, only read/write register access is possible. Configuration, monitoring, alarm handling, protection switching and performance monitoring functions, for example, are therefore controlled via this register access, and the host processor is continuously polling or responding to interrupts from framer, mapper and switch components. All accesses span function calls on the host processor running different applications. While some of the applications are repetitive, others require very tight loops to maintain state information. Operating systems typically run in hundreds of milliseconds based on a task based scheduler. However, transmission functions of the framer/mapper change in the microsecond range (i.e. a standard frame is 125 microseconds). Therefore, there is often a mismatch in the needs of the operating system run by the host processor, forcing the operating system scheduler to run faster to attempt to capture the changes occurring in the framer.
Further, providing framers, mappers and switches separate from the host processor requires more space and unnecessarily consumes board area. For example, the separate devices require large processor buses, and often require external buses which can be used for such things as digital control channels (DCC), break out of overhead for external access, High-Level Data Link Control (HDLC) controllers for packet over SONET applications, Utopia buses, debug ports, different backplane buses, separate cross links for protection switching, etc. Also, there is an increase in the potential for non-compliance to electromagnetic compatibility (EMC) with the additional buses. Finally, additional devices and interconnections increase the ambient or background noise of a card, possibly creating interference levels above acceptable thresholds.
Accordingly, there is a need for an improved programmable logic device and method of employing a processor in a programmable logic device.